1. Field of the Invention
The present invention relates to an internal supply voltage generating circuit, and more particularly, to an internal supply voltage generating circuit with improved reliability despite variable fabrication process steps.
2. Discussion of the Related Art
Generally, a stable voltage at a specific node in a circuit is required for an internal power source. In this case, it is necessary to lower an AC impedance of the node and stabilize the DC voltage level at the node. Since it is difficult to satisfy these two requirements at the same time, only one of these requirements is typically satisfied. For example, the internal power source may be based on the low impedance. A reference voltage generator provides a stable voltage against variable external temperature or variable external voltage. To ensure an excellent internal power source, the low impedance and the reference voltage generator should be considered in designing the internal power source.
Meanwhile, to design a reference voltage generator which provides a stable reference voltage regardless of the variable external voltage and the variable external temperature, the reference voltage should be based on a physical constant. Typical examples of the reference voltage are a built-in voltage of a PN junction and a threshold voltage of a MOS structure.
The built-in voltage and the threshold voltage are suitable for use as the reference voltage. Due to their rare design variables, these voltages depend on process conditions rather than the size of a given device. It is therefore essential that the effect of a temperature variable, i.e., the temperature coefficient, is minimized in designing peripheral circuits. In this respect, various circuits have been proposed.
In one circuit, a reference voltage, which is not affected by the variable external voltage, the variable external temperature, and the variable process steps, is generated. If the internal supply voltage is varied, the varied voltage is detected so that feedback is performed at high speed in response to the detected voltage, thereby reducing the variance of the internal supply voltage. Therefore, the internal power source voltage circuit requires a stable reference voltage generator, a high speed feedback loop, and high capacity current supply ability.
A related internal supply voltage generating circuit will be described with reference to FIG. 1. The internal supply voltage generating circuit shown in FIG. 1 includes a reference voltage generator for generating a reference voltage V.sub.ref from an external supply voltage V.sub.cc, an internal voltage level amplifier for amplifying the reference voltage generated by the reference voltage generator to generate an internal voltage V.sub.LR, and a driver 30 for driving the internal supply voltage V.sub.dd by the value amplified by the internal voltage level amplifier 20.
The reference voltage generator 10 generates a stable reference voltage regardless of fluctuations in the external supply voltage Vcc. The reference voltage generator 10 includes first and second NMOS transistors 11 and 12 having a gate in common, and a resistor 13 having one end connected to a source of the second nMOS transistor 12 and the other end connected to Vss. The reference voltage generator 10 also includes a first pMOS transistor 14 having a drain connected to the common gate of the first and second nMOS transistors 11 and 12, and having a source connected to V.sub.cc. The reference voltage generator 10 further includes a second pMOS transistor 15 having a source connected to Vcc and a drain connected to the source of the second nMOS transistor 12. The gates of the first and second pMOS transistors 14 and 15 are connected to each other. The common gate of the first and second pMOS transistors 14 and 15 is connected to a drain terminal of the second pMOS transistor 15 and provides a reference voltage V.sub.ref.
In the aforementioned reference voltage generator 10, since the first and second pMOS transistors 14 and 15 use the gate in common, current which flows through the first pMOS transistor 14 is the same as that which flows through the second pMOS transistor 15 in a saturation region.
The internal voltage level amplifier 20 includes four pMOS transistors 16, 17, 18, and 19 connected in series between Vcc and Vss. A third pMOS transistor 16 has a gate connected to the reference voltage node of the reference voltage generator 10 and a source terminal connected to V.sub.cc. A fourth pMOS transistor 17 has a source terminal connected to a drain terminal of the third pMOS transistor 16 and a drain terminal connected to its own gate. A fifth pMOS transistor 18 has a source terminal connected to the drain terminal of the fourth pMOS transistor 17 and a drain terminal connected to its own gate. A sixth pMOS transistor 19 has a source terminal connected to the drain terminal of the fifth pMOS transistor 18, and a drain terminal connected to its own gate and to Vss.
The node connecting the drain terminal of the third pMOS transistor 16 and the source terminal of the fourth pMOS transistor 17 is the output node of the internal voltage level amplifier 20 providing the internal voltage V.sub.LR.
The driver 30 includes a comparator 21 for detecting a voltage difference between the internal voltage V.sub.LR output from the output node of the internal voltage level amplifier 20 and the internal supply voltage Vdd. The driver 30 also includes a seventh pMOS transistor 22 having a gate connected to the output of the comparator 21 and a source connected to Vcc. The driver 30 further includes a third nNMOS transistor 23 having a drain connected to the drain of the seventh pMOS transistor 22 and a source connected to Vss. The seventh pMOS transistor 22 and the third nMOS transistor 23 have the common drain which provides the internal supply voltage V.sub.dd, which is also fed back to an input of the comparator 21.
In the reference voltage generator 10 of the internal supply voltage generating circuit shown in FIG. 1, the current which flows in the gate of the first pMOS transistor 14 can be expressed as EQU V.sub.GS1 =V.sub.GS2 +I.multidot.R, (Equation 1)
where V.sub.GS1 is the voltage across the gate and source of the first NMOS transistor 11, and V.sub.GS2 is the voltage across the gate and source of the second nMOS transistor 12. Since the first pMOS transistor 14 and the second pMOS transistor 15 are formed by the same process steps, the following equation can be obtained. ##EQU1##
In this case, the current which flows to the common gate from the saturation region can be expressed as follows. ##EQU2## V.sub.T1 and V.sub.T2 represent threshold voltages for the first and second riMOS transistors 11 and 12, respectively.
Therefore, the following equation is obtained. ##EQU3##
As a result, a current which has no relation to the external power source Vcc flows. Meanwhile, the following equations are obtained. ##EQU4## V.sub.GS4 represents a voltage across the gate and source of the second pMOS transistor 15. V.sub.TP4 represents the threshold voltage for the second pMOS transistor 15.
Therefore, the internal voltage V.sub.LR is expressed as EQU V.sub.LR =3(.vertline.V.sub.tp .vertline.+.alpha.), (Equation 7)
where V.sub.tp represents a threshold voltage for each of the fourth, fifth, and sixth pMOS transistors 17, 18, and 19.
The internal voltage V.sub.LR is generated by amplifying V.sub.tp, which may vary depending on the fabrication process variables and conditions, three times. Accordingly, the internal voltage V.sub.LR depends on the variables of the process steps. The driver 30 functions to keep the internal supply voltage V.sub.dd at the same level as that of the internal voltage V.sub.LR.
The above internal voltage generating circuit has several problems. First, the internal supply voltage level depends on the manufacturing process steps, in particular, burn-in process steps. Since it is impossible to perform exact burn-in process, reliability of a manufactured chip is reduced. In addition, to adjust the internal supply voltage level, a trimming circuit is additionally required.